1. Field of the Invention
The present invention relates generally to oxygen containing plasma etchable layers within microelectronics fabrications. More particularly, the present invention relates to methods for forming patterned oxygen containing plasma etchable layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics integration levels have increased and microelectronics device and conductor element dimensions have decreased, it has become increasingly common within the art of microelectronics fabrication to employ interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor layers within microelectronics fabrications microelectronics dielectric layers formed of low dielectric constant dielectric materials. For the purposes of this disclosure, low dielectric constant dielectric materials are intended as dielectric materials having a dielectric constant of less than about 3.6, while higher dielectric constant dielectric layers formed within microelectronics fabrications employing conventional silicon oxide, silicon nitride and silicon oxynitride dielectric materials typically have dielectric constants in the range of from about 4.0 to about 7.0. Microelectronics dielectric layers formed of low dielectric constant dielectric materials are desirable interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor layers within microelectronics fabrications since such dielectric layers formed from such low dielectric constant dielectric materials provide dielectric layers through which there may be fabricated microelectronics fabrications with enhanced microelectronics fabrication speed, attenuated patterned microelectronics conductor layer parasitic capacitance and attenuated patterned microelectronics conductor layer cross-talk.
Low dielectric constant dielectric materials which may be employed for forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications are typically materials with elevated hydrogen and/or carbon content, such as but not limited to organic polymer spin-on-polymer dielectric materials (such as but not limited to polyimide organic polymer spin-on-polymer dielectric materials, poly (arylene ether) organic polymer spin-on-polymer dielectric materials, and fluorinated poly (arylene ether) organic polymer spin-on-polymer dielectric materials), amorphous carbon dielectric materials (such as but not limited to amorphous carbon and fluorinated amorphous carbon) and silsesqiuoxane spin-on-glass (SOG) dielectric materials (such as but not limited to hydrogen silsesquioxane spin-on-glass (SOG) dielectric materials, carbon bonded hydrocarbon silsesquioxane spin-on-glass (SOG) dielectric materials, and carbon bonded fluorocarbon silsesquioxane spin-on-glass (SOG) dielectric materials).
Silsesquioxane spin-on-glass (SOG) dielectric materials are characterized by the general chemical formula R1--Si(OR2)3, where: (1) R1 may be any of several radicals, including but not limited to hydrogen radical (--H) and carbon bonded organic radicals such as but not limited to carbon bonded hydrocarbon radicals (such as but not limited to methyl radical --CH3) and ethyl radical (--C2H5)) and carbon bonded fluorocarbon radicals (such as but not limited to trifluoromethyl radical (--CF3) and pentafluoroethyl radical (--C2F5)), but not oxygen bonded radicals; and (2) R2 is typically, although not exclusively, a carbon bonded organic radical such as but not limited to a methyl radical (--CH3) or an ethyl radical (--C2H5). Such silsesquioxane spin-on-glass dielectric materials are typically spin-coated and subsequently thermally cured at temperatures of from about 350 to about 420 degrees centigrade to form within microelectronics fabrications low dielectric constant microelectronics dielectric layers.
While organic polymer spin-on-polymer dielectric materials, amorphous carbon dielectric materials, and silsesquioxane spin-on-glass (SOG) dielectric materials are thus desirable within the art of microelectronics fabrication for forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications, organic polymer spin-on-polymer dielectric materials, amorphous carbon dielectric materials, and silsesquioxane spin-on-glass (SOG) dielectric materials are not entirely without problems in forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications. In particular, organic polymer spin-on polymer dielectric materials, amorphous carbon dielectric materials, and silsesquioxane spin-on-glass (SOG) dielectric materials, due to their hydrogen content and/or carbon content, are difficult to pattern with uniform linewidth dimension within advanced microelectronics fabrications through conventional photolithographic methods employing conventional positive or negative photoresist etch mask layers, since when stripping while employing a conventional oxygen containing plasma etch method from such a patterned low dielectric constant microelectronics dielectric layer a conventional positive or negative photoresist etch mask layer which is employed in defining the patterned low dielectric constant microelectronics dielectric layer, there is typically laterally etched the patterned low dielectric constant microelectronics dielectric layer due to susceptibility to etching of the low dielectric constant dielectric material within the oxygen containing plasma etch method.
Laterally etched patterned low dielectric constant microelectronics dielectric layers are undesirable within advanced microelectronics fabrications since when such laterally etched patterned low dielectric constant microelectronics dielectric layers have contact vias or interconnection vias formed therethrough to access semiconductor substrate contact regions or patterned conductor layer contact regions within microelectronics fabrications there is often compromised the linewidth and/or spacing of patterned microelectronics conductor stud layers formed within the contact vias or interconnection vias formed through those laterally etched patterned low dielectric constant microelectronics dielectric layers.
It is thus towards the goal of forming within advanced microelectronics fabrications patterned low dielectric constant microelectronics dielectric layers formed from oxygen containing plasma etchable dielectric materials, with attenuated lateral etching of the patterned low dielectric constant microelectronics dielectric layers when stripping from the patterned low dielectric constant microelectronics dielectric layers patterned photoresist layers employed in defining those patterned low dielectric constant microelectronics dielectric layers that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards forming within advanced microelectronics fabrications patterned microelectronics layers (not necessarily patterned microelectronics dielectric layers) formed of oxygen containing plasma etchable materials with attenuated lateral etching of the patterned microelectronics layers when stripping from the patterned microelectronics layers patterned photoresist layers which are employed in defining those patterned microelectronics layers.
Various photolithographic and etch methods have been disclosed in the art of microelectronics fabrication for forming patterned microelectronics layers within microelectronics fabrications.
For example, Liu in ULSI Technology, C. Y. Chang et al., eds., McGraw-Hill (1996), pp. 446-47, discloses in general various methods for forming within integrated circuit microelectronics fabrications bordered and borderless stacked patterned conductor contact layers. Disclosed are both damascene and non-damascene methods for forming the bordered and borderless stacked patterned conductor contact layers.
Similarly, Korczynski, in "Low-k dielectric integration cost modelling," Solid State Technology, October 1997, pp. 123-28, discloses in general various methods for forming patterned low dielectric constant dielectric layers interposed between the patterns of patterned conductor interconnection layers within microelectronics fabrications. Disclosed are standard patterned conductor metal interconnection formation and isolation methods and dual damascene patterned conductor metal interconnection formation and isolation methods.
In addition, Lin et al., in U.S. Pat. No. 5,246,883, discloses a method for forming a contact via structure through at least one dielectric layer within an integrated circuit microelectronics fabrication. The method employs at least the one dielectric layer having formed thereover a first buffer layer which in turn has formed thereupon a second buffer layer, where the second buffer layer has a higher isotropic etch rate in an isotropic etch method than the first buffer layer. By employing the isotropic etch method for etching the second buffer layer and at least a portion of the first buffer layer, followed by an anisotropic etch method for etching any remainder of the first buffer layer and at least the one dielectric layer, the taper of the sidewall of a via formed through at least the second buffer layer, the first buffer layer and the dielectric layer may be controlled.
Further, Moslehi, in U.S. Pat. No. 5,460,693, discloses a photolithography method for use in fabricating patterned integrated circuit microelectronics layers within integrated circuit microelectronics fabrications, where the photolithography method is undertaken employing dry processing methods only. The completely dry processing photolithography method employs a halogen doped silicon layer or a halogen doped silicon-germanium layer as a photosensitive layer from which is subsequently grown an oxide hard mask layer employed as an etch mask layer when etching a processable integrated circuit microelectronics layer formed below the halogen doped silicon layer or the halogen doped silicon-germanium layer.
Yet further, Havemann, in U.S. Pat. No. 5,565,384, discloses a method for forming within an integrated circuit microelectronics fabrication a self-aligned via through an inorganic dielectric layer to access a patterned conductor layer formed below the inorganic dielectric layer, where the patterned conductor layer has interposed at least partially between its patterns an organic containing dielectric layer. The patterned conductor layer and the organic dielectric layer are completely covered by the inorganic dielectric layer. The method employs an anisotropic etchant which is selective to the inorganic dielectric layer with respect to the organic dielectric layer, such that the organic dielectric layer serves as an etch stop layer when etching the self-aligned via through the inorganic dielectric layer, thus avoiding overetching of the organic dielectric layer.
Still yet further, Shoda, in U.S. Pat. No. 5,529,953, discloses a method for forming within an integrated circuit microelectronics fabrication a void free patterned contiguous interconnection and contact stud layer within a dielectric layer having formed therein an interconnection trench contiguous with but at a different level than a contact via. The method employs forming upon the floor of the interconnection trench a first material which exhibits a first incubation time for forming the patterned contiguous interconnection and contact stud layer thereupon. The method also employs forming upon the floor of the contact via a second material which exhibits a second incubation time for forming the patterned contiguous interconnection and contact stud layer thereupon, where the first incubation time is greater than the second incubation time.
Moreover, Ohsaki, in U.S. Pat. No. 5,677,243, discloses a method for forming an interconnection stud layer within an interconnection via within a dielectric layer within an integrated circuit, where the interconnection via is conventionally formed employing a single etch method while employing a pair of patterned photoresist etch mask layers sequentially overlying the dielectric layer. The method employs a sacrificial organic interconnection via filling layer filled within the interconnection via subsequent to a first etch method within a pair of etch methods, such that the pair of etch methods may be undertaken with separate patterned photoresist layers and thus provide the interconnection stud layer and interconnection via of maximum width.
Finally, Lee et al., in U.S. Pat. No. 5,654,240, discloses a method for forming a patterned conductor contact layer contacting a semiconductor substrate within an integrated circuit microelectronics fabrication, while avoiding trenching within the semiconductor substrate when etching the patterned conductor contact layer from a corresponding blanket conductor contact layer formed contacting the semiconductor substrate. The method employs: (1) a first patterned conductor layer formed upon a patterned dielectric layer formed upon the semiconductor substrate, where the first patterned conductor layer does not contact the semiconductor substrate; and (2) a second patterned conductor layer patterned to terminate upon the first patterned conductor layer while contacting the first patterned conductor layer and the semiconductor substrate.
Desirable within the art of microelectronics fabrication are methods and materials through which there may be formed within microelectronics fabrications patterned microelectronics layers formed of oxygen containing plasma etchable materials, with attenuated lateral etching of the patterned microelectronics layers when stripping from the patterned microelectronics layers patterned photoresist layers employed in defining the patterned microelectronics layers. More particularly desirable within the art of microelectronics fabrication are methods and materials through which there may be formed within microelectronics fabrications patterned low dielectric constant microelectronics dielectric layers formed of oxygen containing plasma etchable low dielectric constant dielectric materials, with attenuated lateral etching of the patterned low dielectric constant microelectronics dielectric layers when stripping from the patterned low dielectric constant microelectronics dielectric layers patterned photoresist layers employed in defining those patterned low dielectric constant microelectronics dielectric layers.
It is towards the foregoing objects that the present invention is both generally and more specifically directed.